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june 2012 doc id 9553 rev 4 1/24 AN1723 application note designing with the l5973ad high efficiency dc-dc converter introduction the l5973ad is a step-down monolithic power switching regulator capable of delivering up to 2 a at output voltages from 1.235 v to 35 v. the operating input voltage ranges from 4.4 v to 36 v. it is realized in bcdv technology and the power switching element is realized by a p-channel d-mos transistor. it doesn?t require a bootstrap capacitor, and the duty cycle can range up to 100%. an internal oscillator fixes the switching frequency at 500 khz which minimizes the lc output filter. the synchronization pin is available in case a higher frequency is required. pulse-by-pulse and frequency foldback overcurrent protection offer an effective short-circuit protection. other features include voltage feed-forward, protection against feedback disconnection, and inhibit and thermal shutdown. the device is housed in a hsop8 package with exposed pad that helps to reduce the thermal resistance junction to ambient (r thj-a ) down to approximately 40 c/w. figure 1. eval5973ad demonstration board www.st.com
contents AN1723 2/24 doc id 9553 rev 4 contents 1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2 lc filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 pwm comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1 positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.2 buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 dual output voltage with auxiliary winding . . . . . . . . . . . . . . . . . . . . . . . . 20 7.4 synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.5 compensation network with mlcc (multiple layer ceramic capacitor) at the output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.6 external soft-start network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AN1723 list of figures doc id 9553 rev 4 3/24 list of figures figure 1. eval5973ad demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 4. demonstration board application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 5. pcb layout (component side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 6. pcb layout (bottom side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 7. pcb layout (front side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 8. junction temperature vs. output current at vin = 5 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 9. junction temperature vs. output current at vin = 12 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 10. efficiency vs. output current at vin = 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 11. efficiency vs. output current at vin = 12 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 12. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 13. error amplifier equivalent circuit and compensation network . . . . . . . . . . . . . . . . . . . . . . . 12 figure 14. module plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 15. phase plot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 16. layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 17. short-circuit current vin = 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 18. short-circuit current vin = 30 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 19. positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 20. buck-boost regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 21. dual output voltage with auxiliary winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 22. synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 23. mlcc compensation network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 24. soft-start network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
pin description AN1723 4/24 doc id 9553 rev 4 1 pin description table 1. pin functions n. name description 1 out regulator output 2 sync master/slave synchronization. when open, a signal synchronous with the turn-off of internal power is present at the pin. when connected to an external signal at a frequency higher than the internal signal, the device is synchronized by the external signal. when connecting the sync pins of two devices together, the one with the higher frequency works as master and the other as slave. 3inh a logical signal (active high) disables the device. with ihn higher than 2.2 v the device is off and with inh lower than 0.8 v, the device is on. if inh is not used, the pin must be grounded. when it is open, an internal pull-up disables the device. 4 comp e/a output to be used for frequency compensation. 5fb step-down feedback input. connecting the output voltage directly to this pin results in an output voltage of 1.235 v. an external resistor divider is required for higher output voltages (the typical value for the resistor connected between this pin and ground is 4.7 k ). 6v ref reference voltage of 3.3 v. no filter capacitor is needed for stability. 7 gnd ground 8v cc unregulated dc input voltage. figure 2. package figure 3. pin connection am11311v1 hsop8-exposed pad out sync inh comp 1 3 2 4 vcc vref gnd fb 8 7 6 5 d98in955 am11310v1
AN1723 application information doc id 9553 rev 4 5/24 2 application information in figure 4 the demonstration board application circuit is shown, where the input supply voltage, v cc , can range from 4.4 v to 25 v due to the rated voltage of the input capacitor, and the output voltage is adjustable from 1.235 v to v cc . figure 4. demonstration board application circuit table 2. component list reference part number description manufacturer c1 10 f, 25 v tokin c2 poscap 6tpb330m 330 f, 6.3 v sanyo c3 c1206c221j5gac 220 pf, 5%, 50 v kemet c4 c1206c223k5rac 22 nf, 10%, 50 v kemet r1 5.6 k , 1%, 0.1 w 0603 neohm r2 3.3 k , 1%, 0.1 w 0603 neohm r3 4. 7 k , 1%, 0.1 w 0603 neohm d1 stps2l25u 2 a, 25 v st l1 do3316p-153 15 h, 3 a coilcraft d0 3 in1454 8 4 5 1 7 l597 3 ad c1 10 f 25v ceramic c2 33 0 f 6. 3 v vout= 3 . 3 v vin = 4.4v to 25v r1 5.6k r2 3 . 3 k r 3 4.7k c4 22nf c 3 220pf 3 l1 15 h d1 s tp s 2l25u comp vcc out fb gnd inh 2 6 3 . 3 v s ync. vref am11 3 12v1
application information AN1723 6/24 doc id 9553 rev 4 figure 5. pcb layout (component side) figure 6. pcb layout (bottom side) figure 7. pcb layout (front side) the graphs that follow show the t j versus output current in different input and output voltage conditions, and some efficiency measurements. am11 3 1 3 v1 42 mm 3 4 mm am11 3 14v1 f am11 3 15v1
AN1723 application information doc id 9553 rev 4 7/24 the following points are analyzed: component selection closing the loop board layout ? thermal considerations ? short-circuit protection application ideas. figure 8. junction temperature vs. output current at v in = 5 v figure 9. junction temperature vs. output current at v in = 12 v 20 3 0 40 50 60 70 8 0 90 100 0.2 0.4 0.6 0. 8 11.21.41.61. 8 2 io(a) tj (c) v o=2.5 v o= 3 . 3 v v o=1. 8 v vi n=5v t a m b =25c 20 3 0 40 50 60 70 8 0 90 100 0.2 0.4 0.6 0. 8 11.21.41.61. 8 2 io(a) tj (c) v o=2.5 v o= 3 . 3 v v o=1. 8 v vi n=5v t a m b =25c am11 3 16v am11 3 17v1 tj ( c) 20 3 0 40 50 60 70 8 0 90 100 110 0.2 0.4 0.6 0. 8 11.21.41.61. 8 2 vi n=12v t a m b =25c v o= 3 . 3 v v o=5v v o=2.5v 20 3 0 40 50 60 70 8 0 90 100 110 0.2 0.4 0.6 0. 8 11.21.41.61. 8 2 vi n=12v t a m b =25c v o= 3 . 3 v v o=5v v o=2.5v tj (c) figure 10. efficiency vs. output current at v in = 5 v figure 11. efficiency vs. output current at v in = 12 v am11 3 1 8 v1 65 70 75 8 0 8 5 90 95 0.2 0.4 0.6 0. 8 11.21.41.61. 8 2 io(a) efficiency ( % ) vin=5v vo u t=2.5v vo u t= 3 . 3 v vo u t=1. 8 v 65 70 75 8 0 8 5 90 95 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 io(a) efficiency ( % ) vin=5v vo u t=2.5v vo u t= 3 . 3 v vo u t=1. 8 v am11 3 19v1 65 70 75 8 0 8 5 90 95 0.20.40.60. 8 1 1.2 1.4 1.6 1. 8 2 io(a) efficiency ( % ) vin=12v vo u t= 3 . 3 v vo u t=2.5v vo u t=5v 65 70 75 8 0 8 5 90 95 0.2 0.4 0.6 0. 8 11.21.41.61. 8 2 io(a) efficiency ( % ) vin=12v vo u t= 3 . 3 v vo u t=2.5v vo u t=5v
component selection AN1723 8/24 doc id 9553 rev 4 3 component selection 3.1 input capacitor the input capacitor must be able to support the maximum input operating voltage and the maximum rms input current. since step-down converters draw current from the input in pulses, the input current is squared and the height of each pulse is equal to the output current. the input capacitor must absorb all this switching current which can be up to the load current divided by two (worst case, with duty cycle of 50%). for this reason, the quality of these capacitors must be very high to minimize the power dissipation generated by the internal esr, thereby improving system reliability and efficiency. the critical parameter is usually the rms current rating, which must be higher than the rms input current. the maximum rms input current (flowing through the input capacitor) is: equation 1 where is the expected system efficiency, d is the duty cycle and i o the output dc current. this function reaches its maximum value at d = 0.5 and the equivalent rms current is equal to i o divided by 2 (considering = 1). the maximum and minimum duty cycles are: equation 2 equation 3 where v f is the freewheeling diode forward voltage and v sw the voltage drop across the internal pdmos. considering the range d min to d max it is possible to determine the max. i rms flowing through the input capacitor. different capacitors can be considered: electrolytic capacitors these are the most commonly used due to their low cost and wide range of rms current ratings. the only drawback is that, considering ripple current rating requirements, they are physically larger than other capacitors. ceramic capacitors if available for the required value and voltage rating, these capacitors usually have a higher rms current rating for a given physical dimension (due to the very low esr). the drawback is their high cost. tantalum capacitor small, good quality tantalum capacitors with very low esr are becoming more available. however, they can occasionally burn if subjected to very high current during charge. therefore, it is better to avoid this type of capacitor for the input filter of the device. they can, however, be subjected to high surge current when connected to the power supply. i rms i o d 2d 2 ? ------------------ ? d 2 ------- + ? = i rms i o d 2d 2 ? ------------------ ? d 2 ------- + ? = d max v out v f + v inmin v sw ? ------------------------------------------ and d v out v f + v inmax v sw ? -------------------------------------------- ==
AN1723 output capacitor doc id 9553 rev 4 9/24 4 output capacitor the output capacitor is very important in order to satisfy the output voltage ripple requirement. using a small inductor value is useful to reduce the size of the choke but increases the current ripple. so, to reduce the output voltage ripple, a low esr capacitor is required. nevertheless, the esr of the output capacitor introduces a zero in the open loop gain, which helps to increase the phase margin of the system. if the zero goes to every high frequency, its effect is negligible. for this reason, ceramic capacitors and very low esr capacitors in general should be avoided. tantalum and electrolytic capacitors are usually a good choice for this purpose. a list of some tantalum capacitor manufacturers is provided in ta b l e 3 . 4.1 inductor the inductor value is very important as it fixes the ripple current flowing through the output capacitor. the ripple current is usually fixed at 20-40% of i omax , which is 0.3-0.6 a with i omax = 1.5 a. the approximate inductor value is obtained using the following formula: equation 4 where t on is the on time of the internal switch, given by d t. for example, with v out = 3.3 v, v in = 12 v and i o = 0.45 a, the minimum inductor value is about 12 h. the peak current through the inductor is given by: equation 5 and it can be observed that if the inductor value decreases, the peak current (which must be lower than the current limit of the device) increases. so, when the peak current is fixed, a higher inductor value allows a higher value for the output current. in ta b l e 4 , some inductor manufacturers are listed. table 3. recommended output capacitors manufacturer series cap value ( f) rated voltage (v) esr (m ) avx tps 100 to 470 4 to 35 50 to 200 kemet t494/5 100 to 470 4 to 20 30 to 200 sanyo poscap (1) tpa/b/c 100 to 470 4 to 16 40 to 80 sprague 595d 220 to 390 4 to 20 160 to 650 1. poscap capacitors have characteristics very similar to tantalum capacitors. l v in v out ? () i -------------------------------------- - t on ? = i pk i o i 2 ---- - + =
output capacitor AN1723 10/24 doc id 9553 rev 4 table 4. recommended inductors manufacturer series inductor value ( h) saturation current (a) coilcraft do3316 15 to 33 2.0 to 3.0 coiltronics up1b 22 to 33 2.0 to 2.4 bi hm76-3 15 to 33 2.5 to 3.3 epcos b82476 33 to 47 1.6 to 2 wurth elektronik 744561 33 to 47 1.6 to 2
AN1723 closing the loop doc id 9553 rev 4 11/24 5 closing the loop figure 12. block diagram 5.1 error amplifier and compensation network the output l-c filter of a step-down converter contributes with a 180 degree phase shift in the control loop. for this reason a compensation network between the comp pin and ground is added. the simplest compensation network together with the equivalent circuit of the error amplifier are shown in figure 13 . rc and cc introduce a pole and a zero in the open loop gain. cp does not significantly affect real system stability, but is useful to reduce the noise of the comp pin. the transfer function of the error amplifier and its compensation network is: equation 6 where a vo = g m r 0 . am11 3 20v1 a o s () a vo 1s r c c c ?? + () ? s 2 r 0 c 0 c p + () r c c c sr 0 c c r 0 c 0 c p + () r c c c ? + ? + ? () 1 + ? + ?? ? ? ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- - =
closing the loop AN1723 12/24 doc id 9553 rev 4 figure 13. error amplifier equivalent circuit and compensation network the poles and zeroes of this transfer function are (if c c >>c 0 +c p ): equation 7 equation 8 whereas the zero is defined as: equation 9 f p1 is the low frequency pole that sets the bandwidth, while the zero f z1 is usually put close to the frequency of the double pole of the l-c filter (see section 5.2 ). f p2 is usually at a very high frequency. 5.2 lc filter the transfer function of the l-c filter is given by: equation 10 am11 3 21v1 f p1 1 2 r 0 c c ?? ? -------------------------------------------------- - = f p2 1 2 r c c 0 c p + () ?? ? --------------------------------------------------------------------- - = f z1 1 2 r c c c ?? ? -------------------------------------------------- = a lc s () r load 1esr c out s ?? () + () ? s 2 lc out esr r load + () sesrc out r load l + ?? () r load + ? + ?? ? ------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------- - =
AN1723 closing the loop doc id 9553 rev 4 13/24 where r load is defined as the ratio between v out and i out . if r load >>esr, the previous expression of a lc can be simplified and becomes: equation 11 the zero of this transfer function is given by: equation 12 f 0 is the zero introduced by the esr of the output capacitor and is very important to increase the phase margin of the loop. the poles of the transfer function can be calculated through the following expression: equation 13 in the denominator of a lc , the typical second order system equation can be recognized: equation 14 if the damping coefficient is very close to zero, the roots of the equation become a double root whose value is n . similarly for a lc , the poles can usually be defined as a double pole whose value is: equation 15 5.3 pwm comparator the pwm gain is given by the following formula: equation 16 where v oscmax is the maximum value of a sawtooth waveform, and v oscmin is the minimum value. a voltage feed-forward is implemented to ensure a constant g pwm . this is obtained generating a sawtooth waveform directly proportional to the input voltage v cc . a lc s () 1 esr c out s ?? + lc out s 2 esr c out s1 + ?? + ?? -------------------------------------------------------------------------------------------------------------------- - = f 0 1 2 esr c out ?? ? ------------------------------------------------------------------ = f plc1 2 , esr c out esr c out ? () 2 4lc out ?? () ? ? () ? 2lc out ?? ------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------- = s 2 2 ? n s 2 n + ?? ? + f plc 1 2 lc out ? ?? ---------------------------------------------------------- = g pwm s () v cc v oscmax v oscmin ? () ------------------------------------------------------------------------ =
closing the loop AN1723 14/24 doc id 9553 rev 4 equation 17 where k is equal to 0.152. therefore the pwm gain is also equal to: equation 18 this means that even if the input voltage changes, the error amplifier does not change its value to keep the loop in regulation, therefore ensuring better line regulation and line transient response. in summary, the open loop gain can be written as: equation 19 example 1 : considering r c = 2.7 k , c c = 22 nf and c p = 220 pf, the poles and zeroes of a 0 are: f p1 = 9 hz f p2 = 256 khz f z1 = 2.68 khz if l = 22 h, c out = 100 f and esr = 80 m , the poles and zeroes of a lc becomes: f plc = 3.39 khz f 0 = 19.89 khz finally r 1 = 5.6 k and r 2 = 3.3 k . the gain and phase bode diagrams are plotted respectively in figure 14 and figure 15 . figure 14. module plot v oscmax v oscmin kv cc ? () = ? g pwm s () 1 k --- - const == gs () g pwm s r 2 r 1 r 2 + --------------------- - a 0 ?? s () a lc s () ? () = am11 3 22v1
AN1723 layout considerations doc id 9553 rev 4 15/24 figure 15. phase plot the cutoff frequency and the phase margin are: f c = 14.9 khz phase margin = 29 . 6 layout considerations the layout of switching dc-dc converters is very important to minimize noise and interference. power-generating portions of the layout are the main cause of noise and so high switching current loop areas should be kept as small as possible and lead lengths as short as possible. high impedance paths (in particular the feedback connections) are susceptible to interference, so they should be as far as possible from the high current paths. a layout example is provided in figure 16 . the input and output loops are minimized to avoid radiation and high frequency resonance problems. the feedback pin connections to the external divider are very close to the device to avoid pickup noise. another important issue is the groundplane of the board. since the package has an exposed pad, it is very important to connect it to an extended groundplane to reduce the thermal resistance junction to ambient. am11 3 2 3 v1
layout considerations AN1723 16/24 doc id 9553 rev 4 figure 16. layout example 6.1 thermal considerations the dissipated power of the device is related to three different sources: switching losses due to the not negligible r dson . these are equal to: equation 20 where d is the duty cycle of the application. note that the duty cycle is theoretically derived from the ratio between v out and v in , but in practice it is quite higher than this value to compensate for the losses of the overall application. for this reason, the switching losses related to the r dson increase compared to an ideal case. equation 21 where t on and t off are the overlap times of the voltage across the power switch and the current flowing into it during the turn-on and turn-off phases. t sw is the equivalent switching time. quiescent current losses equation 22 where i q is the quiescent current. am11 3 24v1 l597 3 ad cin d co u t l inhi b it s ign a l to o u tp u t volt a ge vin vo u t gnd r1 r2 1 4 5 8 very s mall high current circulating path to minimize radiation and high frequency re s onance problem s output capacitor directly connected to heavy ground compen s ation network far from high current path s minimun s ize of feedback pin connection s to avoid pickup connection to groundplane through via s extended groundplane on the bottom s ide p on r dson i out () 2 d ?? = p sw v in i out t on t off + () 2 ---------------------------------------- - f sw ?? ? v in i out t sw f sw ??? == p q v in i q ? =
AN1723 layout considerations doc id 9553 rev 4 17/24 example 2 : v in = 5 v v out = 3.3 v i out = 1.5 a. the r dson has a typical value of 0.25 @ 25 c and increases up to a maximum value of 0.5 @ 150 c. we can consider a value of 0.4 . t sw is approximately 70 ns i q has a typical value of 5 ma @ v in = 12 v. the overall losses are: equation 23 the junction temperature of the device is: equation 24 where t a is the ambient temperature and rth j-a is the thermal resistance junction to ambient. considering that the device, if mounted on the board with a good groundplane, has a thermal resistance junction to ambient (rth j-a ) of about 42 c/w, and considering an ambient temperature of about 70 c: equation 25 6.2 short-circuit protection in overcurrent protection mode, when the peak current reaches the current limit, the device reduces the t on down to its minimum value (approximately 250 ns) and the switching frequency to approximately one third of its nominal value (see the l5973ad device datasheet). in these conditions, the duty cycle is strongly reduced and, in most applications, this is enough to limit the current to i lim . in any case, if there is a heavy short-circuit at the output (v out = 0 v) and depending on the application conditions (v cc value and parasitic effect of external components) the current peak could reach values higher than i lim . this can be understood by considering the inductor current ripple during the on and off phases: on phase equation 26 p tot =r d s on ? ( i out ) 2 ? d ? v in ? i out ? t s w ? f s w ? v in ? i q = =0.4 ? 1.5 2 ? 0.7 ? 5 ? 1.5 ? 70 ? 10 - 9 ? 500 ? 10 3 +5 ? 5 ? 10 - 3 ? 0.9w t j t a rth ja ? p tot ? + = t j 70 0.9 42 108 c ? ? + = i l v in v out dcr l i ? ? ? l ---------------------------------------------------------------- t on ? =
layout considerations AN1723 18/24 doc id 9553 rev 4 off phase equation 27 where v d is the voltage drop across the diode and dcr l is the series resistance of the inductor. in short-circuit conditions, v out is negligible. so, during t off , the voltage applied to the inductor is very small and it is possible that the current ripple in this phase does not compensate for the current ripple during t on . the maximum current peak can be easily measured through the inductor with v out = 0 v (short-circuit) and v cc =v inmax . if the application must sustain the short-circuit condition for an extended period, the external components (mainly inductor and diode) must be selected accordingly. figure 17. short-circuit current v in = 25 v figure 18. short-circuit current v in = 30 v for example, in figure 17 and figure 18 it can be observed that, for a given component list, increasing the input voltage causes the current peak to increase also. the current limit is immediately triggered but the current peak increases until the current ripple during t off is equal to the current ripple during t on . i l v d v out dcr l i ? ++ l -------------------------------------------------------------- - t off ? = am11 333 v1 am11 33 2v1
AN1723 application ideas doc id 9553 rev 4 19/24 7 application ideas 7.1 positive buck-boost regulator the device can be used to design an up-down converter with a positive output voltage. in figure 19 , the schematic circuit of this topology for an output voltage of 12 v is shown. the input voltage can range from 5 v to 35 v. the output voltage is given by v o = v in d/(1-d), where d is the duty cycle. the maximum output current is given by i out = 1 x (1-d). the current capability is reduced by the term (1-d) and so, for example, with a duty cycle of 0.5, and considering an average current flowing through the switch of 1.5 a, the maximum deliverable output current to the load is 0.75 a. this is due to the fact that the current flowing through the internal power switch is delivered to the output only during the off phase. figure 19. positive buck-boost regulator 7.2 buck-boost regulator in figure 20 the schematic circuit to design a standard buck-boost topology is provided. the output voltage is given by v o = -v in d/(1-d). the maximum output current is equal to i out = 1 (1-d), for the same reason as that of the up-down converter. it is important to note that the gnd pin of the device is connected to the negative output voltage. therefore, the device is subject to a voltage equal to v in -v o , which must be lower than 36 v (maximum operating input voltage). vin=5v c1 10 u f 10v cer a mic d1 s tp s 2l25u vcc comp gnd out fb inh s ync vref l597 3 ad 1 3 7 5 6 4 8 2 r 3 4.7k l1 15 u h 24k 2.7k c 3 22nf 3 . 3 v c4 100 u f 16v vout=12v/0.6a c2 220pf d2 s tp s 2l25u m1 s tn4ne0 3 l am11 3 26v1
application ideas AN1723 20/24 doc id 9553 rev 4 figure 20. buck-boost regulator 7.3 dual output voltage with auxiliary winding when two output voltages are required, it is possible to implement a dual output voltage converter by using a coupled inductor. during the on phase, the current is delivered to v out while d2 is reverse-biased. during the off phase, the current is delivered through the auxiliary winding to the output voltage v out1 . this is possible only if the magnetic core has stored sufficient energy. so, to be sure that the application is working properly, the load related to the second output v out1 should be much lower than the load related to v out . figure 21. dual output voltage with auxiliary winding 7.4 synchronization example two or more devices (up to 6) can be synchronized by simply connecting together the synchronization pins. in this case, the device with a slightly higher switching frequency value works as master and those with slightly lower switching frequency values work as am11 3 27v1 d0 3 in1455 8 4 5 1 7 l597 3 ad c1 10 f 10v ceramic c2 10 f 25v ceramic c5 100 f 16v vout=-12v/ 0.6a vin = 5v 2.7k 24k r 3 4.7k c4 22nf c 3 220pf 3 l1 15 h d1 s tp s 2l25u comp vcc out fb gnd inh 2 6 3 . 3 v s ync. vref am11 3 2 8 v1 d0 3 in1456 8 4 5 1 7 l597 3 ad c1 10 f 25v ceramic c5 47 f 10v c4 100 f 10v vout= 3 . 3 v/ 0.5a vout1=5v/ 50ma vin = 5v r 3 4.7k c 3 22nf c2 220pf 3 lp 22 h n1/n2=2 d1 s tp s 25l25u d2 1n414 8 comp vcc out fb gnd inh 2 6 3 . 3 v s ync. vref
AN1723 application ideas doc id 9553 rev 4 21/24 slaves.the device can also be synchronized from an external source. in this case, the logic signal must have a frequency higher than the internal switching frequency of the device (500 khz). figure 22. synchronization example 7.5 compensation network with mlcc (multiple layer ceramic capacitor) at the output mlcc with values in the range of 10 f - 22 f and rated voltages in the range of 10 v - 25 v are available today at relatively low cost from many manufacturers. these capacitors have very low esr values (a few m ), so they are sometimes used for the output filter to reduce the voltage ripple and the overall size of the application. however, the very low esr value affects the compensation of the loop (see section 5 ) and in order to keep the system stable, a more complicated compensation network may be required. figure 23 shows an example of a compensation network which stabilizes the system using ceramic capacitors at the output (the optimum component values depend on the application). figure 23. mlcc compensation network example am11 3 29v1 vcc gnd out fb inh s ync vref 1 3 7 5 6 4 8 2 l597 3 ad comp vcc gnd out fb inh s ync vref 1 3 7 5 6 4 8 2 l597 3 ad comp vin am11 33 0v1 l1 vin=5v c1 mlcc 10uf d1 stps340u vcc comp gnd out fb inh sync vref 1 3 7 5 6 4 8 2 r3=2.2k 4.7uh coilcraft c4=4.7nf c2 mlcc 22uf 6.3v l5973ad vout=2.1v c5=2.7nf r4=470 r1=3.3k c3=220pf r2=4k7 l1 vin=5v c1 mlcc 10uf d1 stps340u vcc comp gnd out fb inh sync vref 1 3 7 5 6 4 8 2 r3=2.2k 4.7uh coilcraft c4=4.7nf c2 mlcc 22uf 6.3v l5973ad vout=2.1v c5=2.7nf r4=470 r1=3.3k c3=220pf r2=4k7
application ideas AN1723 22/24 doc id 9553 rev 4 7.6 external soft-start network at startup, the device can quickly increase the current up to the current limit in order to charge the output capacitor. if a soft ramp-up of the output voltage is required, an external soft-start network can be implemented as shown in figure 24 . the capacitor c is charged up to an external reference (through r), and the bjt clamps the comp pin. this clamps the duty cycle, limiting the slew rate of the output voltage. figure 24. soft-start network example am11 33 1v1 vin vcc comp gnd out fb inh s ync vref 1 3 7 5 6 4 8 2 l597 3 ad vout vref r=4k7 c=2.7nf bc 3 27 vin = 4.4v to 25v vcc comp gnd out fb inh s ync vref 1 3 7 5 6 4 8 2 l597 3 ad vout = 3 . 3 v vref r=4k7 vref r=4k7 c=2.7nf bc 3 27 c1 10 u f 25 cer a mic c4 22nf c 3 220pf r 3 4k7 r1 5k6 r2 4k7 l1 15 u h s tp s3 400 c2 33 0 u f 6. 3 v
AN1723 revision history doc id 9553 rev 4 23/24 8 revision history table 5. document revision history date revision changes 18-oct-2006 2 initial electronic version 09-jun-2009 3 ? section 5: closing the loop modified ? minor text changes throughout the document 07-jun-2012 4 equations: 4 , 5 , 20 , 21 , 22 , 23 , 24 , 25 , 26 and 27 have been updated.
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